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文件名称: 联想thinkpad e431 电路图
  所属分类: 硬件开发
  开发工具:
  文件大小: 2mb
  下载次数: 0
  上传时间: 2019-01-12
  提 供 者: weixin_********
 详细说明：联想thinkpad e431 电路图之前电脑坏了 从网上找了一份 没确认真实性Voltage Rails SIGNAL STATE LP# sLP S3# SLP S4#sLP s5#+vALW+V +ys clock +5vs FUL ON HIGH HIGH HIGH +3vs powe S3【 Suspend t。RaN) HIGH 了GH OFF 十1.svs s4 (Suspend to Disk) HIGH +CPU CORE +1.5V +VGA CORE S5【 Soft OFF LOw +3VM +VCC GFXCORE AXG state +0.75vs +1. CvS BOARD ID Table Bard工D PCB Revis1。n 02 M3suP?。rtd S3 M3 Suppot 5 S4/AC s5 s4/ Battery only S5 S4/Ac Battery con t exist X USB Port Table BOM Structure Table USB 2. 0 Port 3 External Bro Item OM Structure USBp。≌t EC SM Bus1 address EC SM Bus2 address UHc工0 USB 3.0 Port (Left Side 45LEVEL 45 c001 011X b Therr al Sensor Finlek F75303M 1001 10 1xb UHCII USB 3.0 Port (Left Side) NVid⊥ D工s EHCI1 USB 3.0 Port USB3. 0 UHCI2 Touch panel PCH AUX Power +3V PCHO 工 ntel UMA PCH SM Bus address UHCI3 VRAM Option X76 Intel SBA Address SBAC Intel AOAC UHc工4 AOAC 9 USB Port(Right Side) TPM uDH凵MM2 1001 010XI 10 Mini Card(WLAN/BT) GPU N1 4M-GL NL4MGL日 EHC工2 UHc工5 GPU N14P-GV2 N14PGV2G UHCI6L 12 Mini Card(WWAN) SIM Card sl。七 Camera Touch panel Touc Finger Print Board SMBUS Control table SSD SSDC ZZZ SOURCE VGA BATT KESO12 SODIMM WWan sens H MB EC CK1 SMB EC DAI / KBS DA PCB +3VALW A80000TG00 SMB EC CK XXXX XⅩ SMBCLK XXX XX 3VALW SMLOCLK SMLODATA +3VALW XXXxX SML1CLK SML1DATA X XXXx EARCODF 16)7 C ossification Future Center secret Data Notes list Icrc MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT FROF WRIT EN Date: [ jVs PEG ICCMPI and R.]Po sicrals shoul= 9 shorted ard routed 500m11s P=G HCOMFC typical impp anc E rahms 5555b5555555 PCIE_CRX_CTX_N[ 7 22 EG FX#I6 * 1: Normal Operation; Lane defini-ion matches socket pin map definition 15 DMI CTX PRX P3 PCIF_CRX_GTX_PIO 7. 0: Lane Reversed PEG RKIO 155FM 3450 FDI CTX PR) D们 8R1 15 fDI CTX rrx FDO T 15 FDIcTX PEX PA G TAo:Ma PCIE_CTX GRx_N[O71 22 15 FDL CTX PP) FK2E CE CTX GRX R 1 FSYNC 日8 DO LSYNC +1.5Ws s04 PEG CIE_ CTX_GRX_ P[0.7] 22 SDP HPD 上物 」040210V6K eDP_CCMPIo and ICOMPo signals Tx shoulld be shorted near balls d and routed with typical impedance <25 mohms x1s|2 TYCO 20. 0620.2 Y BnIDCE 个 Nvidia support PCIE Gen2 C ossification LC Future Center Secret Data MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT FROF WRIT EN Date: JPU1日 13 H SVB VB#< PROC SEI ECT# 04325 TOCC# 哥入人。,m 1.5vs H PE Prccessor Fullups sM DnAMnET*ARs H CRAVRS TH F2811 8204025%HFeC40 41 H PROCHOT# c 八入八 AL3C \m图[一影 DDR3 HHM I RIP#< THERNTRIP# /PD for JTAG signal 16 H PM SYNC A34 日|Σ ,器 185 CPLPMR:>x、p1^入~2 UNCOREPW RGOOD DM SYS PV/RGC 33221 2130c402 PM CRAM PV/RGD R CBRM PAL3sXDPDBRESE-C I BUF CPU RST RESET# SV Cr VDEC 0.U0421642 儿04216V42 20004025% 16 FN ORAM PWAGD SN7AI C1G07DGKR SGm-5 :90025% For 26 Fin XDP Conn 一+m 1417293940414 PM DRAM R33 PM SYS PWRGD BJF C ossification LC Future Center Secret Data PROCESSOR(2/7)PMDP CLK Icrc MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT FROF WRIT EN A04 Don_A_ D(.c31 bB b t growin A趴AAA M CLK DDR1 1 M CLK DDF3 2 ODR A DO 5 B DER B DOs0.可 日8E 11 CAEs DDR日WE扌 Cn 2013620-. IVY FRInGF TYCO 2013620-2 I/Y BRDGE k_402_57 A-DCR3_DRAMRST# DRAMRST CNTRL >DFAMRST-_CNTRL 3 C ossification LC Future Center Secret Data 47U04[216v4z2 PROCESSOR(3/7 DDRIN Icrc MAY BE USED BY OR DISCLOSED TOANY THIRD PARTY WITHOUT FROF WRIT EN Date: crG straps for processor K_04C21% CC DIE SENSE 1: Nor mal Operation: Lane defirition natches XDr_crGa finit⊥ol eversed CC GE
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