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DFT_clk_mux_and_DFT_clk_chain.pdf
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上传时间: 2020-07-27
详细说明：DFT OCC电路结构以及实现原理
The DFT_clk_mux and DFT_clk_chain are inserted as two separate modules in the top level of the
design, but they always function together as a unit. The DFT_clk_mux is inserted between the OCC
(On-Chip Clocking) clock generator, usually a PLL (Phase-Locked Loop), and its clock tree to
provide control over the clock for scan shifting and capture. The DFT_clk_chain contains data to
control the capture operation of the DFT_clk_mux. These blocks are kept separate because the flipflops
inside DFT_clk_mux must be nonscan to allow them to switch clock sources correctly, but the
flip-flops inside DFT_clk_chain must be on the scan chains so that the capture pulses can be
controlled by ATPG.
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