DE2 web serve的源代码 Overview: - This design is based on the Nios II/f core and provides a typical mix of peripherals and memories as well as a video pipeline. The SOPC Builder system provides an interface to each hardware component on the embedded eva
This is version 1.4 of the MC8051 IP core. November 2004 This design is set up for the Altera Cyclone Nios evaluation board. Changes: - corrected behaviour of RETI instruction handling - added synchronization for interrupt signals - corrected timer
