IEEE Standard for SystemVerilog— Unified Hardware Design, Specification, and Verification Language . IEEE Std 1800™-2012 (Revision of IEEE Std 1800-2009) IEEE 3 Park Avenue New York, NY 10016-5997 USA 21 February 2013 不用多说，懂的人都知道
The definition of the language syntax and semantics for SystemVerilog, which is a unified hardware design, specification, and verification language, is provided. This standard includes support for modeling hardware at the behavioral, register transf
