This application note discusses how to design and implement a Bus Master design using Xilinx® Endpoint PCI Express® solutions. 提供如何使用xilinx endpoint PCI express环境，Application Note: Virtex-6, Virtex-5, Spartan-6 and Spartan-3 FPGA Families
This application note describes how to interface the Virtex®-5 LXT, SXT, TXT, and FXT devices featuring GTP/GTX transceivers to an analog-to-digital (ADC) converter compliant to JEDEC Standard No. 204A (JESD204A) Serial Interface for Data Converters
Since the introduction of the PCI Express® protocol, Xilinx has been the market leader in FPGA-based PCI Express solutions—from the soft IP FPGA logic-based solutions in the Virtex®-II Pro family, to the first Integrated Block for PCI Express in the
Xilinx PCIe 核的官方文档.The LogiCORE™ IP Endpoint Block Plus for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex®-5 LXT/SXT/FXT/TXT FPGA devices. The Endpoint Block Plus for PCI Express
Xilinx FPGA PCIe核用户手册1.14版本。The Endpoint Block Plus core internally instances the Virtex-5 Integrated Endpoint Block. See UG197, Virtex-5 Integrated Endpoint Block for PCI Express Designs User Guide for information about the internal architecture of
