ASIC（专用集成电路） Application-Specific Integrated Circuit. A piece of custom-designed hardware in a chip. 专用集成电路。一个在一个芯片上定制设计的硬件。 address bus （地址总线） A set of electrical lines connected to the processor and all of the peripherals withwhich itcommunicates.
源程序 VHDL 电子时钟 1. 10进制计数器设计与仿真 （1）10进制计数器VHDL程序 --文件名：counter10.vhd。 --功能：10进制计数器，有进位C --最后修改日期：2004.3.20 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter10 is Port ( clk : in st
his project is dedicated to the port of the Free Pascal Compiler to MIPS architecture. Download Now! fpc_mips_all_090a.zip (2.0 MB) OR View all files http://fpc-mips.sourceforge.net This is an attempt to port FPC to MIPS architecture. The source cod
entity OPB_UARTLITE_RX is port ( Clk : in std_logic; Reset : in std_logic; EN_16x_Baud : in std_logic; Use_Parity : in std_logic; Odd_Parity : in std_logic; RX : in std_logic; Read_RX_FIFO : in std_logic; Reset_RX_FIFO : in std_logic; FIFO_Triger :
内含：串口收发程序，I/O口应用程序，模数转换程序，以及初始化等单片机入门应用。是freescale 9S12XE系列单片机入门难得的好资料。-freescale MC9S12XEP100 development board DEMO C language source code. Includes: serial transceiver procedures, I/O port applications, analog-to-digital conversion process, as we
十进制计数器 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count10 is port(clr,start,clk: in bit; cout: out bit; library ieee; daout: out std_logic_vector(3 downto 0)); end count10; architecture a of count10 is signal
