说明: module KEY(CLK, RESET, ADD, MINUS, KEY_IN, SIGN, HOUR_EN, MINUTE_EN, SECOND_EN, KEY_OUT ); //输入输出信号 input CLK; input RESET; input [3:0]KEY_IN; input [1:0]SIGN; output reg ADD; output reg MINUS; output reg HOUR_EN; output reg MINUTE_EN; output reg SE
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