Digital-electronics-1
实验室
标头3
抓这个。 源代码
architecture dataflow of gates is
begin
f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i));
found_o <=
-- fand_o <= a_i and b_i;
-- fxor_o <= a_i xor b_i;
and architecture dataflow;
Digital-electronics-1
实验室
源代码
architecture dataflow of gates is
begin
f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i));
fnand_o <=
-- fand_o <= a_i and b_i;
-- fxor_o <= a_i xor b_i;
end architecture dataflow
