Digital-electronics-1
nadpis druhe urovne
architecture dataflow of gates is
begin
f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i));
fnand_o <=
-- fand_o <= a_i and b_i;
-- fxor_o <= a_i xor b_i;
end architect
Digital-electronics-1
H3文字
源代码
architecture dataflow of gates is
begin
f_o <= ((not b_i) and a_i) or ((not c_i) and (not b_i));
fnand_o <=
--fand_o <= a_i and b_i;
--fxor_o <= a_i xor b_i;
end architecture dataflow;
