Digital-electronics-1
我的实验室
实验室
链接
源代码
f_o <= ( not b_i and a_i) or ( not c_i and not b_i);
f_nand_o <= not ( not ( not b_i and a_i) and not ( not b_i and not c_i));
f_nor_o <= not (b_i or not a_i) or not (c_i or b_i);
Digital-electronics-1
实验室
源代码
begin
writeline ( " Boris voní " );
end ;
摩根法律模拟
architecture dataflow of gates is
begin
f_o <= (( not b_i) and a_i) or (( not c_i) and ( not b_i));
fnand_o <= not ( not (( not b_i) and a_i) and not ((
Digital-electronics-1
zkouska hlavicky 1
zkouska hlavicky 2
斜体粗体
清单1 A B C D gh
清单2
清单2 A B C D 1654
测试
测试2
阿夫萨夫
k
阿斯达斯
A B C D
ukazka kodu
entity gates is
port (
a_i : in std_logic ; -- Data input
b_i : in s
Digital-Electronics-1
实验室
源代码
VHDL语法
entity HelloWorld is
end entity ;
architecture sim of HelloWorld is
begin
process is
begin
report " Hello World! " ;
wait ;
end process ;
end architecture ;
